高速FPGA器件的顶层设计(含外文出处)

高速FPGA器件的顶层设计(含外文出处)(中文12000字,英文8100字)
鸣谢
在开始这份报告之前，我想感谢下面这些人，他们帮助我完成了这个项目，没有他们的帮助，我是不可能完成这个项目。
我要感谢我的主管韦力•拉克教授，他在整个项目进行中给了我很多的建议和鼓励，他还告诉我也面对在项目中遇到的困难。
我要感谢杨教授，他让我运用他的硬件运算法则。他还给我说明的例子源文件好让了解他的理论。我还要谢谢他卓越的多媒体的教程。这些多媒体教程包括了很多让我明白图像进程原理的概念。
我还要感谢阿•塔夫和雪瑞。他们是两个PH•D的研究生，他们在项目执行和应用上帮了我很多。
摘要
在这个项目中，我发现了一个高质量硬件设计的体系方法，有了这个方法，我成功地在高速硬件上运行了一个经典的凝胶图像算法。在这份报告中，我还会提到一个新器件，这种新硬件可以通过重新排列代码来自动完成高质量的硬件优化。这样它可以运行在最小的时钟周期中。这份报告分为5个章节
第一节是介绍：主要包括背景和所有相关的工作，还有一些我在这个项目上投资。
第二节是优化：在这一节中，我将着重描述用于优化的新器件。我还将论证一些器件可以自动优化的过程。
第三节是硬件拓展：在这节中，我将归纳几步改变一个软件，然后下载到硬件中。这些包括许多能改进性能或者保存硬件资源的器件。
第四节是范例分析：凝胶图像过程。在这节中，我将用凝胶图像过程作为一个例子来说明在第二节中讨论的硬件的资源和性能的影响。我还会比较两种器件和软件的应用的性能，软件的版本是：Pilchard 和 RC1000
第五节是结论，包括评估成就和期望的特性工作

High Level Design For High Speed FPGA Devices
Man. Ng mcn99
Department of Computing
Imperial College
June 13, 2002
Acknowledgement
Before starting the report, I would like to thank the following people for helping me throughout the project. Without their help, it would be impossible for me to finish the project:
I would like to thank my supervisor Dr. Wayne Luk for giving me a lot of useful advices and encouragement throughout the project. He also guided me towards the problems I should focus on during the implementation. I would like to thank Professor Yang for letting me to implement his gel-image processing algorithm on hardware. He also gave me references and example sources to understand the theories underneath. And I would like to thank for his teaching in his excellent multimedia course. The course conveyed many useful concepts for me to understand the gel image processing I would like to thank Altaf and Shay. They are two Ph.D research students who helped me a lot throughout the implementation of the application.
Abstract
In the project, I have discovered a systematic approach for high-level hardware design. With this approach, I successfully implemented the sophisticated gel image processing on high speed hardware. In the report, I will also introduced a new technique which can automate the process of high level hardware performance optimization by rearranging the code sequence so that the it can be run at minimum number of clock cycles. The report will be split into 4 Chapters:
Chapter 1 is Introduction. It includes the background, all the related works and my contribution to the project.
Chapter 2 is Optimization. In this chapter, I will focus on the techniques for optimization. I will also demonstrate some techniques which can automate the optimization process.
Chapter 3 is Hardware Development. In this chapter, I will generalize the steps of converting a software programme into hardware. These include several techniques which can improve the performance or save the hardware resources.